Proposal 01-251r0

Richard Moore richard.moore at qlogic.com
Thu Sep 6 16:55:29 PDT 2001


* From the T10 Reflector (t10 at t10.org), posted by:
* Richard Moore <richard.moore at qlogic.com>
*
Here are my final comments on 01-251. As I mentioned earlier I won't be
available to attend next week's meeting.

The problem George Penokie was alluding to in his message last week occurs
when a target that is sending or requesting pad bytes has passed step 4
of the procedure in 10.7.3.3.6 (or the corresponding point in 10.7.3.3.7)
which states "(4) wait until the initiator has responded with all ACK
transitions for the previous data group", and then waits for an offset of
zero (i.e., it waits for all ACK transitions of the data field of the
current data group) before going to steps 5 and 6: "(5) wait at least one
transmit REQ assertion period with P_CRCA transitioning since the last REQ
assertion; (6) negate the REQ signal". The target is inserting an additional
step that is not in the standard.

[Note -- I have used the SPI-4 rev 6 section numbers above. The section
numbers were different in SPI-3 and in earlier SPI-4 revisions.]

Some may be point out that if an initiator processes DT REQ edges in pairs
then this is also an additional step outside of the standard. But, in
answering
whether this could be considered a reasonable implementation, we could
consider
a symmetry argument: If a target has a similar implementation in processing
ACKs,
would the two devices be able to communicate in DT mode? The answer is yes,
provided that the negotiated maximum synchronous offset is something other
than
1. As I stated previously, our designers consciously decided not to support
a DT
offset of 1, and we negotiate down to ST mode in the unlikely event that a
target
insists on such an offset.

I don't know if I can construct a symmetry argument (either pro or con)
concerning the target implementation in the first paragraph, since I don't
know
what the initiator equivalent of "wait for zero offset between steps 4 and
5"
would be. I don't know the details of the target in question but my
understanding
is that it will also wait for zero offset before sending CRC REQs, if there
are no
pad bytes. Although no hang occurs when there are no pad bytes (because a
complete
pair of REQ edges has been sent), this will nevertheless affect performance.

Even though John's 01-251 calls the proposed change a "clarification" it is,
in
fact, a technical change (and should be at least be labeled as such). In
place of
a new technical requirement on initiators, I suggest only adding
recommendations
in SPI-4. This could be done both for initiators and targets. Given the late
stage
of SPI-4 product development, and that it isn't clear how many initiator
designs
would be affected, I think this is a better approach. A change in
requirements,
both for initiator and target, could be considered for SPI-5.

Richard Moore
QLogic Corporation

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