Bus Clear Delay question
lohmeyer at t10.org
Tue Jan 23 13:08:39 PST 2001
* From the T10 Reflector (t10 at t10.org), posted by:
* John Lohmeyer <lohmeyer at t10.org>
Good question. The short answer is 'historical reasons'.
This dichotomy has existed since SASI (circa 1981), except it was slightly
worse then because the SASI BUS CLEAR DELAY was 350 ns (maximum) and the
RESET HOLD TIME was 25 msec (minimum). The hardware engineer at Shugart
Associates who picked these times was being extra conservative because he
believed that some SASI devices would need extra time to completely reset
some internal conditions, especially if software was involved.
A target that violates the BUS CLEAR DELAY causes no harm I can think of
(other than being labeled non-standard) until the 25 msec number is
exceeded. Of course, there would be a whole lot of finger pointing if such
a target were connected to an initiator that violated the 25 msec RESET
At 09:43 AM 1/23/2001, you wrote:
>* From the T10 Reflector (t10 at t10.org), posted by:
>* "Stack, Dick" <dick.stack at intel.com>
>I am seeking clarification on the Bus Clear Delay specification.
>Bus Clear Delay is specified to be a maximum of 800 nSec from assertion of
>RST signal to release of all SCSI bus signals by a device.
>( Reset Delay specifies that RST must be continuously true for 200 nSec
>before a device initiates a reset.)
>RST is specified to be a minimum of 25 uSec.
>Why should a device be required to have all signals released within 800 nSec
>when nothing can happen on the bus until RST is released 24.2 uSec later?
>Why couldn't Bus Clear Delay specify that all device signals must be clear
>prior to release of RST?
>Intel Corp. CO5-138
>15400 NW Greenbrier Pkwy
>Beaverton, OR 97006
>(503) 677-4337 office
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>dick.stack at intel.com
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John Lohmeyer Email: lohmeyer at t10.org
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