Bus Clear Delay question

Stack, Dick dick.stack at intel.com
Tue Jan 23 09:43:22 PST 2001


* From the T10 Reflector (t10 at t10.org), posted by:
* "Stack, Dick" <dick.stack at intel.com>
*
I am seeking clarification on the Bus Clear Delay specification.  

Bus Clear Delay is specified to be a maximum of 800 nSec from assertion of
RST signal to release of all SCSI bus signals by a device.

( Reset Delay specifies that RST must be continuously true for 200 nSec
before a device initiates a reset.)

RST is specified to be a minimum of 25 uSec.  

Why should a device be required to have all signals released within 800 nSec
when nothing can happen on the bus until RST is released 24.2 uSec later?


Why couldn't Bus Clear Delay specify that all device signals must be clear
prior to release of RST?

Dick Stack
Senior Engineer
Intel Corp.   CO5-138
15400 NW Greenbrier Pkwy
Beaverton, OR  97006
(503) 677-4337 office
(503) 870-1260 pager
dick.stack at intel.com


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