Paced timing/protocol clarifications

Day, Brian bday at lsil.com
Thu Feb 8 15:31:15 PST 2001


* From the T10 Reflector (t10 at t10.org), posted by:
* "Day, Brian" <bday at lsil.com>
*
I have a two questions about paced transfers.  Hopefully someone can point
me to where in the Spi-4 draft these are covered (I couldn't find a direct
answer).

1.  SEL behaviour when starting a training sequence after a reselection.
	It's my understanding from section 10.7.2 that the target shall
release the SEL line two system deskews after detecting the assertion of BSY
|from the initiator.  In section 10.8.4.2.2, it states that the target shall
assert SEL two system deskews before asserting REQ.  How soon after
releasing SEL from the reselection phase can a target reassert it to prepare
for training?  Essentially, is there any minimum deassertion time between
those two events?


2.  Ending pacing transfers from DT DATA IN
	From section 10.8.4.3.4, the target negates the REQ and P1 lines
once the offset has gone to zero.  Then it states the rules in 10.13 must be
followed.  Is there any minimum time restriction on the target from negating
the REQ/P1 to changing the phase lines?  If the target is allowed to
simultaneously negate the REQ/P1 and change phase, the initiator may
actually see a REQ in the new phase during that switch if the cable skews
the REQ "slower" than the phase lines... which to the initiator would look
like a violation of section 10.13.    I was expecting to find some
requirement on the target for that, but didn't see one.

Brian Day
LSI Logic Corp.


   


*
* For T10 Reflector information, send a message with
* 'info t10' (no quotes) in the message body to majordomo at t10.org




More information about the T10 mailing list