SPI-4 P1 Line
r_moore at qlc.com
Tue Apr 25 14:31:20 PDT 2000
* From the T10 Reflector (t10 at t10.org), posted by:
* Richard Moore <r_moore at qlc.com>
>From: Gene_Milligan at notes.seagate.com
>[mailto:Gene_Milligan at notes.seagate.com]
>Sent: Tuesday, April 25, 2000 8:36 AM
>To: 't10 at t10.org'
>Subject: Re: SPI-4 P1 Line
>This prevents DC
>for those that think P1 needs to have more margin than data
>bits. I think
>the error detection works even if P1 were to be the same as
>the data bits
>(i.e., DC allowed).
Yes, I agree that error correction will work here (unlike P_CRCA,
an error on which could cause pad bytes to be misinterpreted for data
and still slip past the CRC check). However, bus hangs are a potential
result if a P1 error causes miscounting, which was my rationale behind
using a DC-free code for this signal.
Note that asserting an extra data invalid period does not affect the
bandwidth materially. If gaps are inserted in the data, this will be
done because of FIFO starvation, which means there is a bandwidth
bottleneck at the data source. In the end, the SCSI transfer rate will
average out to match the bandwidth of the source.
-- Richard Moore
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