Reason for the CRC_A extra timing

Richard Moore r_moore at qlc.com
Wed Jun 2 09:00:20 PDT 1999


* From the T10 Reflector (t10 at symbios.com), posted by:
* Richard Moore <r_moore at qlc.com>
*
Gene,

Perhaps the opening phrase of Rob's statement ("With data signals") made
this
statement a bit confusing. The context was a comparison between data
setup/hold
times and P_CRCA setup/hold times (hence the prepositional phrase). I
believe the
"assertion time" reference was to REQ assertion time, not data assertion
time.

The reasoning is that a REQ-to-REQ edge time must be greater than the sum of
the
minimum hold time (REQ-to-Data) and the minimum setup time (Data-to-Req).

 -- Richard Moore
    QLogic Corp.

>-----Original Message-----
>From: Gene_Milligan at notes.seagate.com
>[mailto:Gene_Milligan at notes.seagate.com]
>Sent: Friday, May 28, 1999 11:28 AM
>To: relliott at hobbit.eng.hou.compaq.com
>Cc: t10 at Symbios.COM
>Subject: Re: Reason for the CRC_A extra timing
>
>
>* From the T10 Reflector (t10 at symbios.com), posted by:
>* Gene_Milligan at notes.seagate.com
>*
><<With data signals, the actual assertion period must be larger than
>the data hold plus setup, since the "minimum assertion period" is
>larger than that.With data signals, the actual assertion period must be
>larger than the data hold plus setup, since the "minimum 
>assertion period"
>is larger than that.>>
>
>     Be careful. Your reasoning and conclusion may be correct but the
>citation is not correct. In SPI the assertion period 
>specification applies
>to REQ and ACK but is not applicable to data and parity signals. Only
>setup, hold, and risetime specifications apply to those signals.
>
>Gene
>
>
>*
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