Spec issue on MSE leakage current in SPI-3

Alan Littlewood alanl at lsil.com
Thu Apr 29 18:22:12 PDT 1999


* From the T10 Reflector (t10 at symbios.com), posted by:
* Alan Littlewood <alanl at lsil.com>
*

I think that clamping diodes in the transceiver work just fine on the bus in
practice and do not interfere with normal bus operation.
The big issue is the voltage which can appear on the bus because of misbehaving
terminators, legacy devices etc.  In reality silicon vendors are being asked to
provide transceivers which can tolerate 5.5V for extended periods of time.  So,
in the first place, the 4.1V in the spec. (which I think triggered this
conversation) is meaningless and the spec. should say 5.5V.  Perform the
leakage calculations etc. based on this voltage.
Secondly, now I'm going to stick my neck out, we have got to get rid if this
5.5 Volt requirement.  It causes tremendous grief for the designers (circuits
and process) who spend a ridiculous amount of time trying to meet the UNWRITTEN
5.5V spec.  Taking parallel SCSI forward to new heights of performance will be
held back by the baggage of backward compatibility with "Single Ended" devices.

Alan.


Daniel_F_Smith at notes.seagate.com wrote:

> * From the T10 Reflector (t10 at symbios.com), posted by:
> * Daniel_F_Smith at notes.seagate.com
> *
> Correct me if I'm wrong.  A transceiver, sinking maximum current, can only
> pull 2.85V divided by 110 ohm's worth of current from the bus (25.9mA).  If
> an active terminator were to go "open-loop", then the top of a 110 ohm
> termination impedance would see 5.5V maximum (its input supply running 10%
> high).  Calling that worst case, the max current it could sink would be
> 5.5V divided by 110 ohms, or 50mA.  But of course, the input clamp only
> needs to clamp enough current to get the bus voltage down to Vdd of the LVD
> device.  If the input clamp were to draw enough current to protect itself,
> is that enough to interfere with a normal SE bus transfer?  That's the $64
> question.
>
> "Bill Galloway" <BillG at breatech.com> on 04/29/99 02:44:39 PM
>
> Please respond to BillG at breatech.com
>
> To:   "John Lohmeyer" <lohmeyer at ix.netcom.com>, "T10 Reflector"
>       <t10 at Symbios.COM>
> cc:    (bcc: Daniel F Smith)
>
> Subject:  RE: Spec issue on MSE leakage current in SPI-3
>
> * From the T10 Reflector (t10 at symbios.com), posted by:
> * "Bill Galloway" <BillG at breatech.com>
> *
> John,
>
> In general I agree that the receiver will not care if you clamp the line at
> 3 volts. How hard would you clamp it??? I have seen some older designs that
> could put out allot of current above 3 volts.  Would 100ma damage you??
> Would
> 100ma continuos damage the driver??? How would the impedance discontinuity
> of
> your clamping effect signal integrity, reflections, etc.???
>
> Bill Galloway
> BREA Technologies, Inc.
> P: (281) 530-3063
> F: (281) 988-0358
> BillG at breatech.com
>
> -----Original Message-----
> From: John Lohmeyer [mailto:lohmeyer at ix.netcom.com]
> Sent: Thursday, April 29, 1999 4:34 PM
> To: BillG at breatech.com; T10 Reflector
> Subject: RE: Spec issue on MSE leakage current in SPI-3
>
> I do not want to outlaw old devices.  I just want to make it legal for new
> devices to exist on the same bus.  If my new device tends to clamp signals
> at 3 volts (or a little higher) when an old device trys to drive it higher,
> where is the harm?  The receivers will still see a valid high-level
> (assuming SE) and we should not see such high voltages on LVD.
>
> The 20 uA leakage spec at 4.1V will add a lot of cost and complexity for no
> benefit.
>
> John
>
> --
> John Lohmeyer                  Email: lohmeyer at ix.netcom.com
> LSI Logic Corp.                Voice: +1-719-533-7560
> 4420 ArrowsWest Dr.              Fax: +1-719-533-7036
> Colo Spgs, CO 80907              BBS: +1-719-533-7950
>
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