Spec issue on MSE leakage current in SPI-3

mshepher at us.ibm.com mshepher at us.ibm.com
Thu Apr 29 15:14:52 PDT 1999


* From the T10 Reflector (t10 at symbios.com), posted by:
* mshepher at us.ibm.com
*


Please take me off this mail list....

Thanks,

   Michael Shepherd




"Gingerich, Kevin" <k-gingerich at ti.com> on 04/29/99 12:37:20 PM

To:   T10 Reflector <t10 at Symbios.COM>
cc:    (bcc: Michael Shepherd/Austin/IBM)
Subject:  RE: Spec issue on MSE leakage current in SPI-3





* From the T10 Reflector (t10 at symbios.com), posted by:
* "Gingerich, Kevin" <k-gingerich at ti.com>
*
VCC is not a signal defined by the standard.

-----Original Message-----
From: John Lohmeyer [mailto:lohmeyer at ix.netcom.com]
Sent: Thursday, April 29, 1999 12:01 PM
To: T10 Reflector
Subject: Spec issue on MSE leakage current in SPI-3


* From the T10 Reflector (t10 at symbios.com), posted by:
* John Lohmeyer <lohmeyer at ix.netcom.com>
*
One of our circuit designers has noticed that the leakage current spec for
MSE in SPI-3 (Table 16 on page 50) says that the 20 uA maximum leakage
applies from local ground to 4.1 V.  In SPI-2 rev 14 this specification was
over the range of local ground to Vcc.  Does anyone remember why this upper
parameter was changed from Vcc to 4.1 V?  We would like to change this spec
range back to local ground to Vcc in SPI-3.

John


--
John Lohmeyer                  Email: lohmeyer at ix.netcom.com
LSI Logic Corp.                Voice: +1-719-533-7560
4420 ArrowsWest Dr.              Fax: +1-719-533-7036
Colo Spgs, CO 80907              BBS: +1-719-533-7950

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