FW: Spec issue on MSE leakage current in SPI-3

Daniel_F_Smith at notes.seagate.com Daniel_F_Smith at notes.seagate.com
Thu Apr 29 12:22:08 PDT 1999


* From the T10 Reflector (t10 at symbios.com), posted by:
* Daniel_F_Smith at notes.seagate.com
*
Where does 3.7V for SE devices for Voh come from?  Don't most SE drivers
shut off as they approach termination voltage?   Ground offset is expected
to be 4.1V - 3.7V = 400mV.  Is that where the 355mV ground offset came from
in the Annex A system level table?

I'm assuming this entire discussion is revolving around the fact that LVD
I/O is contributing to the SE characteristics while the bus is in SE mode.
I'd like to see the committee address the cross purposes of all the tables
in the front of section 7.  The information is confusing at best.  I don't
think I'm the only one that has trouble interpreting what Ioz and Voh goes
with whatever mode of operation and how this affects other modes.  Anybody
else join me on this point?





"Aloisi, Paul" <aloisi at unitrode.com> on 04/29/99 11:37:14 AM

To:   "'SCSI Reflector'" <t10 at Symbios.COM>
cc:    (bcc: Daniel F Smith)

Subject:  FW: Spec issue on MSE leakage current in SPI-3




* From the T10 Reflector (t10 at symbios.com), posted by:
* "Aloisi, Paul" <aloisi at unitrode.com>
*
John,

MSE controllers often only have 3.3 volts and can be 2.5 volt in the
future,
it was a concern that the signal could be above the local Vcc. The LVD
signals are spec'ed -0.5 to 4.1 volts and single ended drivers can drive to
3.7 volts plus the ground offset. Vcc was considered too low of a voltage,
if it is a 2.5 volt supply plus/minus tolerance.

Vcc of 3.3 volts by the JEDEC battery spec can be 3.0 to 3.6 volts.

Paul

-----Original Message-----
From: John Lohmeyer [mailto:lohmeyer at ix.netcom.com]
Sent: Thursday, April 29, 1999 1:01 PM
To: ALOISI at MSMAILGW.UICC.COM
Subject: Spec issue on MSE leakage current in SPI-3


* From the T10 Reflector (t10 at symbios.com), posted by:
* John Lohmeyer <lohmeyer at ix.netcom.com>
*
One of our circuit designers has noticed that the leakage current spec for
MSE in SPI-3 (Table 16 on page 50) says that the 20 uA maximum leakage
applies from local ground to 4.1 V.  In SPI-2 rev 14 this specification was
over the range of local ground to Vcc.  Does anyone remember why this upper
parameter was changed from Vcc to 4.1 V?  We would like to change this spec
range back to local ground to Vcc in SPI-3.

John


--
John Lohmeyer                  Email: lohmeyer at ix.netcom.com
LSI Logic Corp.                Voice: +1-719-533-7560
4420 ArrowsWest Dr.              Fax: +1-719-533-7036
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