Spec issue on MSE leakage current in SPI-3

Daniel_F_Smith at notes.seagate.com Daniel_F_Smith at notes.seagate.com
Thu Apr 29 11:55:51 PDT 1999


* From the T10 Reflector (t10 at symbios.com), posted by:
* Daniel_F_Smith at notes.seagate.com
*
Vcc is not defined and that's exactly the problem.
Because of 3.3V devices on the bus, the spec needs to address bus operation
at lower Vdd voltages and pay heed to the fact that future bus requirements
will probably need to define the upper end of Vdd expectations. Otherwise,
the silicon designers will always be fighting these expansive voltage
ranges that are required for legacy voltage tolerance.  Why are we
expecting the silicon designers to work miracles when we know the physics
are very difficult for what are supposed to be fairly inexpensive devices?
I don't know where 4.1V came from but it is obviously higher than the 3.63V
which any 3.3V device could possibly expect to generate on the bus.
Besides, if LVD devices are current mode devices, why are we concerned
about the bus being driven to levels that are HIGHER than the Vdd of the
driving devices?  Termination today is limited to 2.85V, which is well
within the operating region of 3.3V devices.  Do we expect termination to
go higher?  I don't think so. If anything, we should be trying to limit all
bus swings as low as we can tolerate in order to reduce power consumption.
If we expect to go at Ultra4 rates, we should address these concerns now,
before silicon designers are expected to perform still another miracle
which may prove impossible.




"Gingerich, Kevin" <k-gingerich at ti.com> on 04/29/99 10:37:20 AM

To:   T10 Reflector <t10 at Symbios.COM>
cc:    (bcc: Daniel F Smith)

Subject:  RE: Spec issue on MSE leakage current in SPI-3




* From the T10 Reflector (t10 at symbios.com), posted by:
* "Gingerich, Kevin" <k-gingerich at ti.com>
*
VCC is not a signal defined by the standard.

-----Original Message-----
From: John Lohmeyer [mailto:lohmeyer at ix.netcom.com]
Sent: Thursday, April 29, 1999 12:01 PM
To: T10 Reflector
Subject: Spec issue on MSE leakage current in SPI-3


* From the T10 Reflector (t10 at symbios.com), posted by:
* John Lohmeyer <lohmeyer at ix.netcom.com>
*
One of our circuit designers has noticed that the leakage current spec for
MSE in SPI-3 (Table 16 on page 50) says that the 20 uA maximum leakage
applies from local ground to 4.1 V.  In SPI-2 rev 14 this specification was
over the range of local ground to Vcc.  Does anyone remember why this upper
parameter was changed from Vcc to 4.1 V?  We would like to change this spec
range back to local ground to Vcc in SPI-3.

John


--
John Lohmeyer                  Email: lohmeyer at ix.netcom.com
LSI Logic Corp.                Voice: +1-719-533-7560
4420 ArrowsWest Dr.              Fax: +1-719-533-7036
Colo Spgs, CO 80907              BBS: +1-719-533-7950

*
* For T10 Reflector information, send a message with
* 'info t10' (no quotes) in the message body to majordomo at symbios.com
*
* For T10 Reflector information, send a message with
* 'info t10' (no quotes) in the message body to majordomo at symbios.com




*
* For T10 Reflector information, send a message with
* 'info t10' (no quotes) in the message body to majordomo at symbios.com





More information about the T10 mailing list