FW: Spec issue on MSE leakage current in SPI-3

Aloisi, Paul aloisi at unitrode.com
Thu Apr 29 11:37:14 PDT 1999


* From the T10 Reflector (t10 at symbios.com), posted by:
* "Aloisi, Paul" <aloisi at unitrode.com>
*
John,

MSE controllers often only have 3.3 volts and can be 2.5 volt in the future,
it was a concern that the signal could be above the local Vcc. The LVD
signals are spec'ed -0.5 to 4.1 volts and single ended drivers can drive to
3.7 volts plus the ground offset. Vcc was considered too low of a voltage,
if it is a 2.5 volt supply plus/minus tolerance.

Vcc of 3.3 volts by the JEDEC battery spec can be 3.0 to 3.6 volts.

Paul 

-----Original Message-----
From: John Lohmeyer [mailto:lohmeyer at ix.netcom.com] 
Sent: Thursday, April 29, 1999 1:01 PM
To: ALOISI at MSMAILGW.UICC.COM
Subject: Spec issue on MSE leakage current in SPI-3


* From the T10 Reflector (t10 at symbios.com), posted by:
* John Lohmeyer <lohmeyer at ix.netcom.com>
*
One of our circuit designers has noticed that the leakage current spec for
MSE in SPI-3 (Table 16 on page 50) says that the 20 uA maximum leakage
applies from local ground to 4.1 V.  In SPI-2 rev 14 this specification was
over the range of local ground to Vcc.  Does anyone remember why this upper
parameter was changed from Vcc to 4.1 V?  We would like to change this spec
range back to local ground to Vcc in SPI-3.

John


--
John Lohmeyer                  Email: lohmeyer at ix.netcom.com
LSI Logic Corp.                Voice: +1-719-533-7560
4420 ArrowsWest Dr.              Fax: +1-719-533-7036
Colo Spgs, CO 80907              BBS: +1-719-533-7950

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