99-119 revision 4

Gary Dickinson g_dickinson at qlc.com
Wed Apr 28 11:03:17 PDT 1999


* From the T10 Reflector (t10 at symbios.com), posted by:
* Gary Dickinson <g_dickinson at qlc.com>
*
Gentlemen,

I think that "Figure x1 - Protection code generator" is incorrect.
The schematic has a misplaced XOR term. The schematic does not match 
the C-Code implementation. 

The following "ASCII" schematic matches the C code example.  The
"X" represents an XOR term.

               <-- Codeword Bits Shift Left        
       +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    +--|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
    |  +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
    V   
    X--------+--------------+-----------+
    ^        |              |           |
    |  +--+  V  +--+--+--+  V  +--+--+  |  
    +--| 5|<-X<-| 4| 3| 2|<-X<-| 1| 0|<-+  
       +--+     +--+--+--+     +--+--+     
          <-- Check Bits Shift Left


The following is a parallel implementation in Verilog that
matches the C code and the corrected schematic.  I have verified
that all possible 15 bit code words produce the same Check Bits
as the C code.  I have also verified that this algorithm matches
the Error Detection Properties mentioned in x1.3:

1.  All errors of 3 bits or less are detected
2.  All odd number of bit errors detected
3.  Better than 98% of all errors are detected.


// Verilog Implementation of Protection Code generator
// Algorithm extracted from T10/99-119r4
//
//   Input: MS    - 15 bit Code word
// Returns: ASYNC - 6 Check bits
//
function [05:00] ASYNC;
input    [14:00] MS;
begin

    ASYNC[00] = MS[00] ^ MS[01] ^ MS[02] ^ MS[03] ^
                MS[05] ^ MS[06] ^ MS[07] ^ MS[10] ^
                MS[11] ^ MS[13];
    ASYNC[01] = MS[01] ^ MS[02] ^ MS[03] ^ MS[04] ^
                MS[06] ^ MS[07] ^ MS[08] ^ MS[11] ^
                MS[12] ^ MS[14];
    ASYNC[02] = MS[00] ^ MS[01] ^ MS[04] ^ MS[06] ^
                MS[08] ^ MS[09] ^ MS[10] ^ MS[11] ^
                MS[12];
    ASYNC[03] = MS[01] ^ MS[02] ^ MS[05] ^ MS[07] ^
                MS[09] ^ MS[10] ^ MS[11] ^ MS[12] ^
                MS[13];
    ASYNC[04] = MS[02] ^ MS[03] ^ MS[06] ^ MS[08] ^
                MS[10] ^ MS[11] ^ MS[12] ^ MS[13] ^
                MS[14];
    ASYNC[05] = MS[00] ^ MS[01] ^ MS[02] ^ MS[04] ^
                MS[05] ^ MS[06] ^ MS[09] ^ MS[10] ^
                MS[12] ^ MS[14];

end
endfunction // ASYNC

Best Regards,


Gary Dickinson

QLogic Corporation
3454 Harbor Blvd.
Costa Mesa, CA 92626
Tel: 714 668-6638
FAX: 714 668-6616
email: g_dickinson at qlc.com
*
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