Endianess of CRC

Edward A. Gardner eag at ophidian.com
Fri May 29 12:14:29 PDT 1998


* From the T10 (formerly SCSI) Reflector (t10 at symbios.com), posted by:
* "Edward A. Gardner" <eag at ophidian.com>
*
Bruce, you need to specify the bit order, not just the byte order, as well
as such details as polynomial, complements, etc.  See FC-PH annex N for an
example of how to specify this unambiguously (and yes, it needs this much
detail).

FYI, while I can come up with at least two ways to interpret your message,
each of them is a different CRC calculation (over the same data) from that
used by Fibre Channel.  (Perhaps I have a malicious sense of humor, I was
sorely tempted to keep silent on this until everyone had committed to
different silicon :-).

Edward A. Gardner               eag at ophidian.com
Ophidian Designs                719 593-8866 voice
1262 Hofstead Terrace           719 593-8989 fax
Colorado Springs, CO  80907

-----Original Message-----
From: Bruce Leshay <Bruce.Leshay at QNTM.COM>
To: 'T10 at symbios.com' <T10 at Symbios.COM>
Date: Friday, May 29, 1998 12:40 PM
Subject: Endianess of CRC


>* From the T10 (formerly SCSI) Reflector (t10 at symbios.com), posted by:
>* Bruce Leshay <Bruce.Leshay at qntm.com>
>*
>The order of the CRC bytes transmitted on the bus was brought up as an
issue
>at the Spi-3 Working Group meeting on 5/22.  I think we should treat both
>the data (for the purposes of the CRC calculation) and the CRC as
big-endian
>quantities.  This is consistent with CDB data, (examples are the LBA and
>XFRLEN fields) which are big-endian.
>
>Imagine the CRC generator/checker as a black box with a 32 bit input and a
>32 bit output.  If on a wide SCSI bus,
>and two words are transferred word0[15:0] first, then word1[15:0].  Then
for
>generating/checking the CRC, the correspondence between the bus data and
and
>the crc input is:
>
>word0[7:0]   <-> CRC_input[31:24]
>word0[15:8] <-> CRC_input[23:16]
>word1[7:0]   <-> CRC_input[15:8]
>word1[15:8] <-> CRC_input[7:0]
>
>Then when the CRC_output[31:0] is transmitted over the scsi bus, it should
>be transmitted in word2 and word3:
>
>CRC_output[31:24] <-> word2[7:0]
>CRC_output[23:16] <-> word2[15:8]
>CRC_output[15:8]   <-> word3[7:0]
>CRC_output[7:0]     <-> word3[15:8]
>
>This may seem confusing, but it's really just renaming of fields.
>
> Bruce Leshay
> Quantum Corporation
>
>*
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