SPI-2 Issues - for Plenary vote in September

Kevin Gingerich k-gingerich at ti.com
Sat Aug 30 20:49:20 PDT 1997


* From the T10 (formerly SCSI) Reflector (t10 at symbios.com), posted by:
* Kevin Gingerich <k-gingerich at ti.com>
*
Regarding Issue 1 raised by Paul, I don't recall doing any circuit analysis 
to justify the maximum 0.5 pF capacitance imbalance specification in SPI-2. I
do recall thinking at the time that good cables exhibit a 2% to 3% 
capacitance imbalance and that the spec was in line with that tolerance. 

An analysis is provided in TIA/EIA RS485 that concludes the differential 
noise voltage, en, can be approximated by en = ei x Yd/(2Gs) where, ei is the
common-mode noise voltage, Yd is the sum of the difference in admittance to 
ground of the two input terminals of each receiver, and Gs is the source 
admittance (even though G is generally assigned to conductance). The 
admittance difference on one receiver from a 0.5 pF capacitance difference at
40 MHz is 125.6 umhos. The source admittance is that of the cable and is 
8.33 mmhos. We are allowing 120 mV of common-mode noise voltage out of a 
transmitter. Doing the math gives a differential noise voltage of 0.9 mV from
one receiver imbalance. Fifteen receivers, all with the same imbalance in the
same direction, would induce 13.6 mV of differential noise from that source. 

Admittedly, the probability of fifteen receivers all with the same imbalance 
is pretty small but, the transmitter common-mode output voltage will not be 
the only source of common-mode noise either. In addition, if the noise was at
120 MHz and a receiver responded that fast, the worst-case noise would triple
to 40.7 mV. As usual, the challenge will be for the working group to agree to
the assumptions and then allocate the 55 mV budgeted for noise to the various
sources. 

One more thought on the proximity effects mentioned in Paul's message, one of
the beauties of balanced signaling is that external influences tend to effect
both lines more or less equally because they are next to each other. Twisting
and careful layout should make proximity effects manageable. I don't think 
keeping the capacitance difference below 0.5 pF impossible but, measuring it 
is problematic. I would input a sine wave to both terminals of the pair, 
measure the difference voltage created, and calculate the admittance 
difference. 

I wouldn't go to this length if I were able to attend the meeting in Nashua. 
I hope it helps and good luck.

/Kevin/

Kevin Gingerich                         Texas Instruments, Inc.
Member- Technical Staff                 P.O. Box 660199 MS8710
Semiconductor Group                     Dallas, TX 75266-0199

v: (972)480-3378    f: (972)761-5265    e: k-gingerich at ti.com

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Original text
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Original text

From: "Paul D. Aloisi 603-429-8687 aloisi at unitrode.com" 
<ALOISI at unitrode.com>, on 8/25/97 8:20 PM:
* From the T10 (formerly SCSI) Reflector (t10 at symbios.com), posted by:
* "Paul D. Aloisi 603-429-8687 aloisi at unitrode.com" <ALOISI at unitrode.com>
*
SPI-2 Issues For the September working Group and Plenary Vote

Issue 1:

The 0.5 pF balance capacitance for LVD SCSI (Table 29 SPI-2R13) and HVD SCSI
(Table 36 SPI-2R13) are extremely hard meet 
for a proto type and impossible to meet in production.  Measuring the parts 
2-3 Controller, Terminator (Maybe) and 
connector with the etch board to 0.5 pF is an impossible task. The 
components have different capacitance reading which 
are effected by the ground plane and the proximity to cables or metal 
objects to the module will change the capacitance, 
as much as several pFs and the difference between lines can be much greater 
than 0.5 pF.

Terminator parts vary 0.5 pF depending on how they are mounted.
BGA controllers have reported 0.6 pF differences in pin capacitance.
The connector has different capacitance from the difference between the 
sides of the connectors.

A controller that has two connectors, terminator and the controller is 
harder to balance than a device with a single 
connector.

At least 1 pF would give a designer the possibility of hitting balance, but 
would be hard to guarantee over 
manufacturing tolerances. The proximity of cables and metal will change the 
capacitance more than the allowed balance. 2 
pF would be possible, with all the components considered.

Table 29 and 36 |C1-C2| (pF) should be increased to 1 pF minimum, 2 pF would 
be better. 



Issue 2:
Terminator current differences between SCSI-2 and SPI/Fast-20 don't allow 
the use of  SCSI-2 terminators for SPI and 
Fast-20 applications.  The SCSI-2 specification is 22.4 mA at 0.5 Volts, the 
SPI/Fast-20 is 24 mA measured at 0.2 Volts. 
The SCSI-2 terminator measured at 0.2 Volts can be as high as 25.4 mA.

SPI-2R13 Section 7.1.1 b
Each terminator shall source current to the signal line whenever its 
terminal voltage is below 2.5 V D.C. and this 
current shall not exceed 24 mA for any line voltage above 0.2 V D.C. even 
when all other signal lines are driven at 4.0 
V D.C.

Change to:
Each terminator shall source current to the signal line whenever its 
terminal voltage is below 2.5 V D.C. and this 
current shall not exceed 22.4 mA for any line voltage above 0.5 V D.C. and 
25.4 mA for any line voltage between 0.5 and 
0.2 V D.C. even when all other signal lines are driven at 4.0 V D.C.



The purposed SE termination I/V were not agreed to, these changes must go in 
standard at a minimum. The I/V curve could 
be added later if agreement can be reached.

 Thank you,

Paul Aloisi
Unitrode


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