Fast-20 HVD timing

Kevin Gingerich k-gingerich at ti.com
Thu Aug 28 17:52:05 PDT 1997


* From the T10 (formerly SCSI) Reflector (t10 at symbios.com), posted by:
* Kevin Gingerich <k-gingerich at ti.com>
*

--BeyondBoundary_15_Thu_Aug_28_17:52:06_1997__26E9
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Mike, although not explicitly stated in Fast-20, the timing requirements apply
at the device connector. The timing budget behind the connector is left up to
the implementor. The timing budget shown in Annex A is only an example of how
it might be done for set up and hold timing. A similar example could be shown
that has a minimum assertion or negation period out of the controller 5 ns
longer than the requirement at the connector to account for pulse skew (or
duty-cycle distortion as you describe it). 

Kevin Gingerich				Texas Instruments, Inc.
Member- Technical Staff			P.O. Box 660199 MS8710
Semiconductor Group			Dallas, TX 75266-0199

v: (972)480-3378    f: (972)761-5265    e: k-gingerich at ti.com

------------------
Original text

From: mham at hamm.engr.sgi.com (Mike Ham), on 8/25/97 5:53 PM:
* From the T10 (formerly SCSI) Reflector (t10 at symbios.com), posted by:
* mham at hamm.engr.sgi.com (Mike Ham)
*
I have some questions about the Fast-20 timing requirements as they apply to an
HVD subsystem.  I am going through the signal integrity and timing margin
portion of a design and am confused as to the timing requirements for REQ and
ACK asserted and negated on the HVD interface.

For data setup and hold, the HVD setup and hold was made to match the SE setup
and hold by reducing the host adapter setup and hold requirements when
operating in an HVD environment.  This compensates for the 5ns part to part
delay scew of the HVD tranceivers.

For REQ and ACK asserted or negated, it doesn't appear that this has been done.
 The HVD tranceivers have a 5ns duty cycle skew.  Since the only note
associated with the REQ and ACK asserted or negated timing refers to the single
ended threshhold requirements, it appears that if you are measuring these
timings at the HVD side of the tranceiver, you must add 5ns to the Fast-20
timing requirement to be in spec.  Is this true?  Thanks for any help you can
provide.

-- 
Mike Ham
mham at engr.sgi.com
*
* For T10 Reflector information, send a message with
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--BeyondBoundary_15_Thu_Aug_28_17:52:06_1997__26E9--
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