LVD SCSI Termination Questions
Walter Bridgewater x2371
wally at eng.adaptec.com
Fri Mar 1 19:29:30 PST 1996
* From the SCSI Reflector, posted by:
* wally at eng.adaptec.com (Walter Bridgewater x2371)
*
note: included question has been shorten, response below.
> * From the SCSI Reflector, posted by:
> * Siegfried.Schmalz at dalsemi.com (Siegfried Schmalz)
>
> QUESTIONS REGARDING THE LVS SCSI BUS TERMINATION AS
> DESCRIBED IN SPI-2 REV 04 (JANUARY 23, 1996)
>
> REGARDING: TERMINATION BALANCE TEST
> ###################################
>
> On pages 17-18, a "Termination Balance Test" is described.
> Questions:
>
> 2. In Figure 6 "Termination balance test configuration", delta_V
> is defined as (V-) - (V+) at the termination for the test
> circuit shown. Table 3 says that this parameter may not
> exceed +/-10mV when the test voltage is swept over its specified
> range. Has this changed since the draft spec was written?
> Or has the termination balance test been modified? If not,
> I believe some of the proposed termination configurations
> would fail the test. The HSPICE deck below uses one
> of the proposed terminations, and its delta_V stays right at
> 70.5mV +/-.02mV with these ideal elements. Could it be that
> that the delta_V is actually defined so that instead of
> delta_V = (V-) - (V+), we define Vdif = (V+) - (V-), and define
> delta_V as the *variation* of Vdif as the test voltage is swept?
> In other words, in the HSPICE deck below, 70.5mV would be Vdif
> and .02mV would be delta_Vmax (or delta_Vmin) in this particular
> simulation with ideal elements.
> Or am I misunderstanding the test altogether?
>
> The following HSPICE run illustrates my question.
> ------------------------------------------------------------------------------
> *** one of the proposed termination schemes ***
> vtop top 0 dc 1.5
> vbot bot 0 dc 1.0
> rtop top minusig 240
> rmid minusig plusig 130
> rbot plusig bot 240
> ***************************
>
> rx1 minusig com 100.01
> rx2 plusig com 99.99
> vsw com 0 dc 0
>
> .dc vsw 0.6 1.8 0.1
>
> .print dc
> + vdif=par('v(plusig)-v(minusig)')
>
> .end
>
> ****** dc transfer curves tnom= 27.000 temp= 27.000
>
> volt vdif
>
> 600.00000m -70.5119m
> 1.80000 -70.4880m
>
> ***** job concluded
> ------------------------------------------------------------------------------
>
> Siegfried Schmalz
>
> Dallas Semiconductor
> schmalz at dalsemi.com
> (214) 450-3764
>
Siegfried and scsi reflector members,
Your observation is very good, I think you have pointed out a problem
with the spec.
Even if you modify the spice deck to be an "ideal" terminator, such as:
vvref vref 0 dc 1.2500
vtop top rref dc 0.057500
vbot rref bot dc 0.057500
rtop top minusig 55.00
rmid vref rref 125.00
rbot plusig bot 55.00
rx1 minusig com 100.00
rx2 plusig com 100.00
you still have an -74.2mv offset.
And this is why:
Let vt = v(rref) + vtop & vb = v(rref) - vbot where v(rref) is the voltage
on the rref node.
Then,
v(minusig) = (rx1 / (rx1 + rtop)) * vt
v(plusig) = (rx2 / (rx2 + rbot)) * vb
to find vdif, subtract v(plusig) for v(minussig) and simplify.
Since rx1 = rx2 & rtop = rbot & vb - vt = -0.115mv , you get a constant
value for the answer:
v(plusig) - v(minusig) = (100 ohms / 155 ohms) * -0.115mv or,
vdif (delta_V) is always = -74.193548 milli Volts.
The same thing is happening in your circuit, although the analysis
is a little more complex, the results are exactly the same. I found this
out by doing some hspice runs, which lead me to the above analysis.
I don't think this was taken into account for the spec, and ALL
terminators that have the 'fail-safe' offset will fail the test
as written now.
Or else, I'm reading it incorrectly too, and it
is what you say it is at the end of your question #2.
If this is so, we then could use this analysis to be the start of a
basis to fill in the delta_V value range for the last row of Table 3.
By directly spec'ing a value for delta_V, the delta_V min/max parameters
could be eliminated, which are confusing things now.
Regards,
Wally
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