SPI-2/Fast-40 pins

Tak Asami asami at dt.wdc.com
Mon May 22 08:48:59 PDT 1995

Jim Mcgrath of Quantum said:
> Drive ASICs today are limited by pinouts more often that gate counts. 
> This means that every pin added has the potential to increase ASIC cost.

Absolutely true.

> But why use anything other than single ended for the other lines?  
> They should work find at the slow speeds required, and at lengths at 
> least good to 6 m (maybe longer).

I tend to agree with that point, too.  Since we are only speeding up the
data transfer phases, BSY, SEL, RST, MSG, C/D, I/O, ATN pins should work
fine.  And depending on the implementation (I've seen some weird and wicked
ones before), differential handshaking like arbitration and selection,
not to mention SCAM, can make things complicated.

On the other hand, I think data lines and parity needs to be differential
just as much as REQ/ACK.  This is unfortunate, since there are 18 of these
pins, but
i) Data lines are moving at at least half the data rate, i.e., presumably
   20MHz for rumored Fast-40. This is just as fast as Fast-20 REQ/ACK today,
   and if we want to extend the cable length any more than what Fast-20 
   single ended specifies, we will need to do something about it.
ii) Data lines must keep the setup and hold timing relationship with REQ/ACK.
   If we drive it through different flavor of drivers at that kind of 
   frequency, it is difficult to guarantee that margin.

For that reason, I would propose to specify differential drivers for REQ, ACK,
Data and Parity lines, and single ended for everything else.

                           Tak Asami
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