Tak Asami (Asami
asami at dt.wdc.com
Wed Jun 1 08:40:07 PDT 1994
Gerry Houlder writes:
> I agree with Jeff Stai's position. The existing words put 100 ns as a lower
> limit (on the period) that cannot be exceeded, and the upper limit is
I agree with what he says, in terms of what SPI document specify today.
I am not so sure if that was the right thing to do.
If 100.0nsec is the absolute minimum cycle time on the SCSI bus, then
assuming you are using +/-250ppm (there you go again) crystal as the
reference clock, YOU MUST NOT DESIGN a target or an initiator that operates
at 10.000MHz clock, or 100.0nsec. You must use 9.998MHz crystal so that
in the worst (best?) case of +250ppm frequency, you are still 10.000MHz.
If you used a 10.000MHz crystal, then half your product have just violated
Or, if you did it *RIGHT* (try to find a 9.998MHz crystal), your nominal
performance is somewhat less than 10MXfr/sec.
Is this what we wanted ultimately? I'll shut up if it is.
Tak Asami ================================================================
Western Digital Corp
I/O Product Engineering
E-mail: asami at dt.wdc.com
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