Mode-less Ata Timings
Tom Hanan (714)932-7472
HANAN_T at a1.wdc.com
Sat Jan 8 00:42:00 PST 1994
The discussion over why we should or should-not continue to extend the
data transfer performance of ATA via discreet timing modes has come up
again.
To help those who may not have been present, or remember why we chose this
methodology, here is a brief refresher.
1) Mode-less timing definitions promote timing flexibility
at the cost of inter-operability. If you do not identify a well
defined set of timing parameters it is almost impossible
to predict the inter-operability of multiple products with
different setup, hold and recovery times within a given system.
Modes are intended to limit the number of these timing sets (modes)
to a manageable (Characterizable) number.
2) Mode-less timing makes it very hard for the retail channel to
match peripherals and systems of similar performance.
Today system integrators use Mode 3 to identify drives, IDE
interface cards, and system BIOS capable of Enhanced IDE
data transfer rates.
Mode-less timings would blur that distinction and their faith
in the flexibility and inter-operability of ATA.
3) Mode-less timings will not eliminate customized OEM solutions.
It is hard to imagine that some OEM's would not push peripherals
past the timing modes that the manufacturer can guarantee to be
inter-operable across the industry.
Pushing the limits in a controlled scenario where the system and
peripheral are well defined and characterized is nothing new. The
thought of doing this without the proper characterization is
however a little scary to the very OEMs who are know best for
doing this. They know that state of the art performance requires a
greater attention to details than an off the shelf design.
The bottom line is simple. The concept of standardizing inter-operable
timing modes has maintained ATA's ease of use at a given performance.
Custom configurations are integrated using device specific information
obtained via a dialog with the peripheral manufacturer and
characterization testing performed by the integrator.
There is nothing implicit in the concept of inter-operable timing modes
which prevents or limits the integration of faster peripherals in well
designed and characterized systems.
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_/ _/ _/_/_/ _/_/_/ Western Digital Corporation
_/ _/ _/ _/ _/ _/ Tom Hanan
_/_/_/_/ _/ _/ _/ Ph. 714 932-7472, Fax. 714 932-7312
_/ _/ _/_/_/ _/_/_/ E-Mail hanan_t at a1.WDC.com
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