From: Hale Landis@SEAGATE X3T9.2/93-110r4 Date: 11-04-93 08:42:30 PM Subject: DMA Definitions -- Round #4 (the final round!) I am bringing the following ATA DMA Definition Round #4 paper to the ATA Extensions WG meeting in Colorado Springs on Monday, 8 Nov 93. (((I have made arrangements to have the room locked with only bread and water available until we reach agreement on this stuff. We have been discussing this stuff for about 4 months now on and off without reaching consensus and I think we are all getting tired of it. So lets get it over with!))) This material was originally prepared as if it were going to be a comment against ATA 4.0. However, as I now feel ATA 4.0 is "dead", this should be considered input for the ATA-2 document. In order to reduce(?) confusion, the section number references in this paper are still the ATA 4.0 section numbers. The following list of issues is basically the same as the Round #2 list presented at the 28 July 93 meeting and the Round #3 list prepare for, but not discussed, at the 29 September 93 meeting. Please note that only one person has responded to my invitation/request for suggestions on any of these problems! --- The Round #4 Updated Issues List --- This list prepared for the 8 Nov 93 ATA Extension WG meeting in Colorado Springs. But first, we have never come to agreement as to what the term "data transfer phase" means for DMA commands. I recommend that this term be defined as meaning the time starting when the DMA command is written into the Command register and ending when the drive asserts INTRQ and the completion of the DMA command. Here is my update list of issues by ATA section number: * 6.3.9 DMARQ -- The definition of DMARQ must be changed. I recommend replacing the text of the first paragraph of this section with the following text: | This signal, used for DMA data transfers between host and | drive, shall be asserted by the drive when it is ready to | transfer data to or from the host. The direction of data | transfer is controlled by DIOR- and DIOW-. If the drive is | not selected, or if the drive is selected and no DMA command is | in progress, this output is in a high impedance state. | | This signal is used in a handshake manner with DMACK-, i.e., | the drive shall wait until the host asserts DMACK- before | negating DMARQ, and re-asserting DMARQ if there is more data | to transfer. * 9 Command descriptions -- This section describes what happens when one command is interrupted by another command. It is not possible to interrupt a Read DMA or Write DMA command with another command. The only way to interrupt a DMA command is with a reset. I recommend the following be added to the end of this section: | The only way to interrupt a Read DMA or Write DMA command is | with a reset. The result of interrupting a Read DMA or Write | DMA command by writing a new command into the Command register | is unpredictable. * 9.9.12 Word 52: DMA data transfer cycle timing mode -- If words 62 or 63 are used or if the drive supports multiword mode 1+, what value should be placed into word 52? I recommend that word 52 be defined as the Single Word DMA transfer cycle timing mode. * 9.15 Read DMA -- I recommend that the second paragraph of this section be replaced with the following text: | During the DMA data transfer phase of a Read DMA command, the | drive shall provide status of BSY or DRQ. | | At command completion, the Command Block Registers contain the | sector address of the last sector read. | | An unrecoverable error encountered during the execution of a | Read DMA command results in the termination of data transfer | at the sector where the error was detected. All, part or none | of the data for the sector in error is transferred. At | command completion, the Command Block Registers contain the | sector address of the sector where the error occurred. * 9.22 Set Features -- The relationship between Set Feature 03H and the Read/Write DMA commands is unclear. Are DMA commands disabled until a Set Feature 03H command is executed? The DMA commands and the Set Feature command are optional. Must a drive implement Set Feature if it implements the DMA commands? * 9.28 Write DMA -- I recommend that the second paragraph of this section be replaced with the following text: | During the DMA data transfer phase of a Write DMA command, the | drive shall provide status of BSY or DRQ. | | At command completion, the Command Block Registers contain the | sector address of the last sector written. | | An unrecoverable error encountered during the execution of a | Write DMA command results in the termination of data transfer | at the sector where the error was detected. All, part or none | of the data for the sector in error is transferred. At | command completion, the Command Block Registers contain the | sector address of the sector where is error occurred. * 10.5 DMA Data Transfer Command -- I recommend the that the text of this section be replaced by the following text: | 10.5 DMA data transfer commands (optional) | | This class comprises: | | - Read DMA | - Write DMA | | Data transfers using DMA commands differ in two ways from PIO | transfers: | | - data transfers are performed using the slave-DMA channel | - a single interrupt is issued at the completion of the command | | Initiation of the DMA transfer commands is identical to the | Read Sector or Write Sector commands except that the host | initializes the slave-DMA channel prior to issuing the | command. | | The interrupt handler for DMA transfer is different in that no | intermediate sector interrupts are issued on multi-sector | commands. | | a) The host writes any required parameters to the Features, | Sector Count, Sector Number, Cylinder and Drive/Head | registers. | b) The host initializes the slave-DMA channel. | c) The host writes the command code to the Command register. | d) The drive sets BSY. | e) When the drive is ready to transfer data, the drive | asserts DMARQ. The DMA data transfer may be split | into several partial transfers at the discretion | of the drive or slave-DMA channel. The drive shall | assert either BSY or DRQ during the entire DMA data | transfer phase. | f) When the drive has completed processing, it clears both | BSY and DRQ and asserts INTRQ. The host reads the | Status register. | g) The host resets the slave-DMA channel. * 10.5.1 Normal DMA Transfer -- I recommend that the diagram be replaced with the following diagram: | +-a)---+-b)-------+-c)----+-d)---+-e)-----+-f)---+-g)--+ | |Setup |Initialize|Issue | |DMA data|Status|Reset| | | |DMA |Command| |transfer| |DMA | | +------+----------+-------+------+--------+------+-----+ | | |BSY=0 |BSY=0 |BSY=1 |BSY=1 |BSY=0 | | | | | | | |or |Assert| | | | | | | |DRQ=1 |INTRQ | | * 10.5.2 Aborted DMA transfer -- I recommend that the diagram be replaced with the following diagram: | +-a)---+-b)-------+-c)----+-d)---+-e)-----+-f)---+-g)--+ | |Setup |Initialize|Issue | |DMA data|Status|Reset| | | |DMA |Command| |transfer| |DMA | | +------+----------+-------+------+--------+------+-----+ | | |BSY=0 |BSY=0 |BSY=1 |BSY=1 |BSY=0 | | | | | | | |or |Assert| | | | | | | |DRQ=1 |INTRQ | | * 10.5.3 Aborted DMA command -- I recommend that the diagram be replaced with the following diagram: | +-a)---+-b)-------+-c)----+-d)---+-f)---+-g)--+ | |Setup |Initialize|Issue | |Status|Reset| | | |DMA |Command| | |DMA | | +------+----------+-------+------+------+-----+ | | |BSY=0 |BSY=0 |BSY=1 |BSY=0 | | | | | | | |Assert| | | | | | | |INTRQ | | -- Hale Landis (Hale_Landis@notes.seagate.com) ------------------------------------------------------------------------- Seagate Technology - 920 Disc Drive - Scotts Valley, CA 95066 USA Main Phone 408-438-6550 - Email Problems postmaster@notes.seagate.com Technical Support: BBS 408-438-8771 Fax 408-438-8137 Voice 408-438-8222 -------------------------------------------------------------------------