Date: Jan 28, 1993 X3T9.2/93-022 rev 0 To: X3T9.2 Committee (SCSI) From: Tom Hanan Subject: SFF Local Bus Meeting Minutes NOTE - THIS IS NOT AN X3T9.2 ACTIVITY. THESE MINUTES ARE PROVIDED COURTESY OF THE SMALL FORM FACTOR COMMITEE TO KEEP MEMBERS OF X3T9.2 APPRISED OF THIS ACTIVITY. ***************************************************************** SFF Local Bus ATA Working Group Meeting Minuets ***************************************************************** The meeting was formally started at 10am to allow as many participants as possible to be present. In all, 16 people from 13 companies attended. Company Contact Phone Fax ----------------------------------------------------------------- Apian Ken Curt 408 730-5406 408 730-5473 Apple Dennis Pak 408 974-4874 408 974-2898 Cirrus Logic John Geldman 510 226-2368 510 226-2150 Cirrus Logic Joseph Chen 510 226-2101 510 226-2170 Conner Steve Anderson 303 682-8320 303 772-0182 Emulex Mehran Ramazani 714 688-5331 Emulex Phil Rafnel 714 688-5435 IBM Dan Colegrove 507 286-5558 507 286-5089 Maxtor Ron Roberts 408 432-3875 408 432-3773 Micronics Chuang Li 510 651-2300 510 651-9450 National Semi. Robbie Shergill 408 721-7959 408 721-7956 Quantum Jim McGrath 408 894-4504 408 894-3208 Segate Gene Milligan 405 324-3070 405 324-3794 TI Dean Wallace 214 997-5973 214 997-5962 Western Digital Tom Hanan 714 932-7472 714 932-7314 Western Digital Shishir Shah 714 932-7235 The meeting started with an overview of the VESA and PCI Buses. The overviews were followed by a discussion where the following buses were identified for review. The objective of the review was to identify which buses should be considered by the group when identifying required features for Local Bus IDE Protocol, Adapters and Drives. The buses identified were: - VESA - PCI - PCMCIA - Card Bus - New Bus - Sbus The conclusion of the group after reviewing the list was that the list could be divided into true Local CPU buses and high performance Memory & I/O buses. The group also noted that while all of these buses were potential candidates for high performance AT drives VESA, PCI and New Bus represented the most immediate market for high performance AT IDE drives. The group also recognized that VESA represented the most pressing short term need as evidenced by several existing proprietary VESA solutions to enhance existing AT IDE drive performance. These conclusions resulted in an agreement among those present to divide the effort into more than one set of goals. Initially the group would focus on incremental enhancements using the existing 40 pin cable, followed at a later date by work on revolutionary designs based on new cables and pinouts. All present agreed that the initial recommendations for 40 pin local bus compatibility should be released by June. The group agreed that this short time frame probably meant that we would need to release the recommendations as an SFF specification until ATA extensions is ready for release as a standard. The group then focused on identifying goals for itself, I.E. deliverables. The result of that discussion was a straw vote with all present agreeing on the following goals: (IBM Abstained) - Timing & Performance Enhancements - ATA Protocol Changes - Behavioral Model of Adapter and Cable At this point the focus of the meeting shifted to identifying goals for the incremental enhancements. The following goals were discussed: - Vendor Independent Performance between 5 and 20MB/s. - Reliable Negotiation of Drives Max. Transfer Rates. - Compatibility with existing PIO & DMA O/S Drivers. - Backward compatibility of Local Bus Compatible Drives with existing AT IDE ports. From these goals a list of potential enhancements were developed to address Reliability, Compatibility and Performance issues. The following enhancements were discussed: (Cirrus) - Additional ATA Timing Modes for PIO w/o IOCHRDY (Cirrus) - New ATA Timing Mode Word for PIO with IOCHRDY (Cirrus) - Additional ATA Timing modes for DMA (TI) - Signal Quality Enhancement - Termination - Active Negation of IOCHRDY - Glitch Removal / Filtering - AC Driver Characterization and Specification (Appian) - Decoupling Local Bus from IDE Timing (WD) - Enhanced Error Reporting - Transfer Underflow (Reads) - Transfer Overflow (Writes) The names to the left of each potential enhancement represent the company which agreed to act as the focal point for outside work done for the next meeting. Based on the amount of work identified it was agreed that the next meeting should take place one month latter. A review of everyone's schedule resulted in the choice of Wed. Feb. 24th @9:30am. Jim McGrath of Quantum agreed to host the next meeting at Quantum's San Jose Facility. Again, because time is critical, the meeting in San Jose will be an SFF working group meeting. For directions to Quantum you can reach Jim at 408 894-4504. Contact: Tom Hanan (Western Digital) 8105 Irvine Center Drive. Irvine, Ca. 92718 Ph. 714 932-7472 Fax 714 932-7314