To:       Membership of X3T9.2                  X3T9.2/92-221R0
From:     John Geldman, Cirrus Logic
Re:       Resolution of Multiword DMA Timing issues in ATA 3.1 / 3.2
Date:     November 12, 1992

On November 10th, representives from Adaptec, Cirrus Logic, Emulex, National
Semiconductor, Seagate, and Western Digital held a discussion during the
X3T9.2 working group meetings.  The purpose was resolve a change made to the
multi-word DMA timing specification tJ based on the comments received from 
Mehran Raitezani of Emulex during the public review period for AT Attachment. 
 
In the comments, tJ described the hold on the DMACK- signal from the trailing
edge of DIOR-/DIOW-.  The value for this specification was 0 ns.

In AT Attachment document revisions 3.1 and 3.2, tJ described the hold on the
DMACK- signal from the leading edge of DIOR-/DIOW-.  The value for this
specification was 0 ns.

The meaning and intention of the tJ specification was reviewed.  Both of the
signals DMACK- and DIOR-/DIOW- are driven by the system.  An example of system
specifications is the timing of DMACK- hold in the EISA type B Burst cycles. 
This is specified at 100 ns and 155 ns from the trailing edge of the
DIOR-/DIOW- signal to the trailing edge of the DMACK- signal for read and
write cycles, respectively. 

In many implementations, the DMACK- signal is used as an enable during the DMA
access cycle.  This requires that the AT Attachment document specify the
timing from the trailing edge of the DIOR-/DIOW- signal.  Furthermore, since
at least 100 ns of hold time is available, it was proposed that the
specification be 20ns.  This will provide margin for the drive electronics. 
The group was in unanimous agreement that the AT Attachment document should
be modified to reflect these conclusions.
The following is the suggested modifications to the AT Attacment document. 
 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

                   |<------------- t0 --------------->|
            ________________________________________________            __
 DMARQ  ___/                                                \__________/
                   |                                  |<--->|
                   |                                  |  tL
               ______________________________________________________ 
 DMACK- ______/                                                      \________/
              |<-->|         |                        |         |
                tI |<-- tD ->|<-------- tK ---------->|         |<-->|
                   |         |                        |         | tJ
 DIOR-             |_________|                        |_________|
 DIOW-  ___________/         \________________________/         \_________
 
                   |<--->|   |
 READ                 tE  ________                           ________
 DD0-15 -----------------<________>-------------------------<________>----
 
                             |<-->|
                             | tF
 WRITE                 ____________                       ____________
 DD0-15 --------------<____________>---------------------<____________>---
 
                      |<---->|<--->|
                         tG    tH

                     +----------------------------+-----------+
                     | Multiword DMA              |   Mode 0  |
                     | Timing Parameters          |    nsec   |
                     |                            | Min | Max |
               +-----+----------------------------+-----+-----+
               | t0  | Cycle Time                 | 480 |     |
               | tC  | DMACK to DMREQ Delay       |     | --- |
               | tD  | DIOR-/DIOW-      16-bit    | 215 |     |
               | tE  | DIOR- Data Access          |     | 150 |
               | tF  | DIOR- Data Hold            |   5 |     |
               | tF  | DIOR- Data Hold            |     |  20 |
               | tG  | DIOW- Data Setup           | 100 |     |
               | tH  | DIOW- Data Hold            |  20 |     |
               | tI  | DMACK to DIOR-/DIOW- Setup |   0 |     |
               | tJ  | DIOR-/DIOW- to DMACK Hold  |  20 |     |
               | tKr | DIOR- Negated Pulse Width  |  50 |     |
               | tKw | DIOW- Negated Pulse Width  | 215 |     |
               | tLr | DIOR- to DMREQ Delay       |     | 120 |
               | tLw | DIOW- to DMREQ Delay       |     |  40 |
               +-----+----------------------------+-----+-----+
                  FIGURE 11-4:  MULTIWORD DMA DATA TRANSFER