BSR X3.*** X3T9.2/92-157r5 Proposed Changes for LBA support for ATA I/F ATA (AT Attachment) September 21, 1992 Western Digital Corporation Shishir Shah Changes proposed to ATA specification REV 3.0 to support Logical Block Addressing Mode at ATA I/F are described below. The sections affected by these changes are described as follows: 7.1.2 Environment The drives using this interface shall be programmed by the host computer to perform commands and return status to the host at command completion. When two drives are daisy chained on the interface, commands are written in parallel to both drives, and for all except the Execute Diagnostics command, only the selected drive executes the command. On an Execute Diagnostics command addressed to Drive 0, both drives shall execute the command, and Drive 1 shall post its status to Drive 0 via PDIAG-. Drives are selected by the DRV bit in the Drive/Head Register (see 7.2.8), and by a jumper or switch on the drive designating it as either a Drive 0 or as Drive 1. When DRV=0, Drive 0 is selected. When DRV=1, Drive 1 is selected. When drives are daisy chained, one shall be set as Drive 0 and the other as Drive 1. When a single drive is attached to the interface it shall be set as Drive 0. Prior to the adoption of this standard, some drives may have provided jumpers to indicate Drive 0 with no Drive 1 present, or Drive 0 with Drive 1 present. Throughout this document, drive selection always refers to the state of the DRV bit, the position of the Drive 0/Drive 1 jumper or switch, or use of the CSEL pin. ******************************** ADDITION STARTS ************************* ATA Drive can operate in CHS or LBA Mode on command by command basis. When Host programs ATA I/O registers, it can select LBA mode of operation by setting "L" bit in Drive/Head register. When "L" bit in Drive/Head register is set Sector number, Cylinder low, Cylinder High and HS3-HS0 of Drive/head register contains the zero based LBA. ATA Drive/controller that supports LBA mode reports LBA support bit = 1 in identify data. LBA is defined as Logical Block Address. In LBA mode address of sectors on the drive are assumed to be linearly mapped with Inital definition LBA 0 = Cylinder 0, Head 0 and sector 1. Irrespective of translate mode geometry set by the host, LBA address of given sector does not change. LBA = [ {Cylinder * (#of Heads} + Heads ] * Sectors/Track + Sector - 1. ******************************** ADDITION ENDS ************************* 7.2 I/O Register Descriptions Communication to or from the drive is through an I/O Register that routes the input or output data to or from registers (selected) by a code on signals from the host (CS1FX-, CS3FX-, DA2, DA1, DA0, DIOR- and DIOW-). The Command Block Registers are used for sending commands to the drive or posting status from the drive. The Control Block Registers are used for drive control and to post alternate status. Table 7-1 lists these registers and the addresses that select them. Logic conventions are: A = signal asserted N = signal negated x = does not matter which it is TABLE 7-1: I/O PORT FUNCTIONS/SELECTION ADDRESSES +----------------------------+---------------------------------------------+ | Addresses | Functions | |CS1FX-|CS3FX-| DA2| DA1| DA0| READ (DIOR-) | WRITE (DIOW-) | +------+------+----+-----+---+-----------------------+---------------------+ | Control Block Registers | +------+------+----+----+----+-----------------------+---------------------+ | N | N | x | x | x | Data Bus High Imped | Not used | | N | A | 0 | x | X | Data Bus High Imped | Not used | | N | A | 1 | 0 | x | Data Bus High Imped | Not used | | N | A | 1 | 1 | 0 | Alternate Status | Device Control | | N | A | 1 | 1 | 1 | Drive Address | Not used | +------+------+----+----+----+-----------------------+---------------------+ | Command Block Registers | +------+------+----+----+----+-----------------------+---------------------+ | A | N | 0 | 0 | 0 | Data | Data | | A | N | 0 | 0 | 1 | Error Register | Features | | A | N | 0 | 1 | 0 | Sector Count | Sector Count | *| A | N | 0 | 1 | 1 | Sector Num/LBA Byte 0 | Sector Num/LBA Byte0| | *| A | N | 1 | 0 | 0 | Cyl Low / LBA Byte 1 | Cyl Low / LBA Byte 1| *| A | N | 1 | 0 | 1 | Cyl High / LBA Byte 2 | Cyl High/ LBA Byte 2| *| A | N | 1 | 1 | 0 | Drive/Head/Mode | Drive/Head/Mode | | A | N | 1 | 1 | 1 | Status | Command | | A | A | x | x | x | Invalid Address | Invalid Address | +------+------+----+----+----+-----------------------+---------------------+ 7.2.3 Cylinder High Register In CHS Mode this register contains the high order bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number. The most significant bits of the cylinder address shall be loaded into the cylinder high Register. *In LBA Mode this register contains the bits 23_16 (Byte 2) of the 28 bit LBA *for any disk access. At the end of the command, this register is updated to *reflect the current LBA bits 23_16 ( Byte 2 ). NOTE: Prior to the introduction of this standard, only the lower 2 bits of this register were valid, limiting cylinder address to 10 bits i.e. 1,024 cylinders. 7.2.4 Cylinder Low Register In CHS Mode this register contains the low order 8 bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number. *In LBA Mode this register contains the bits 15_8 (Byte 1) of the 28 bit LBA *for any disk access. At the end of the command, this register is updated to *reflect the current LBA bits 15_8 (Byte 1). 7.2.8 Drive/Head Register This register contains the drive and head numbers. The contents of this register define the number of heads minus 1, when executing an Initialize Drive Parameters command. 7 6 5 4 3 2 1 0 +-------+-------+-------+-------+-------+-------+-------+-------+ * | 1 | L | 1 | DRV | HS3 | HS2 | HS1 | HS0 | +-------+-------+-------+-------+-------+-------+-------+-------+ *- L is the binary encoded mode select. This bit selects CHS vs LBA mode. * When L = 0, Sector number, Cylinder Low, Cylinder High and HS3-HS0 * of Drive/Head Register indicates CHS value. * When L = 1, Drive Sector Number, Cylinder Low, Cylinder High and HS3-HS0 * of Drive/head registers have LBA bits 7_0 (Byte 0), LBA bits 15_8 (Byte 1), * LBA bits 23_16 (Byte 2) and LBA bits 27_24 respectively. * NOTE: * This bit is valid only for following commands * * Command OPCODE * * Read DMA (w/retry) C8h * Read DMA (w/o retry) C9h * Read Multiple C4h * Read Sector(s) (w/retry) 20h * Read Sector(s) (w/o retry) 21h * Read Long (w/retry) 22h * Read Long (w/o retry) 23h * Read Verify Sector(s) (w/retry) 40h * Read Verify Sector(s) (w/o retry) 41h * Seek 7xh * Write DMA (w/retry) CAh * Write DMA (w/o retry) CBh * Write Multiple C5h * Write Same E9h * Write Sector(s) (w/retry) 30h * Write Sector(s) (w/o retry) 31h * Write Long (w/retry) 32h * Write Long (w/o retry) 33h * Write Verify 3Ch - DRV is the binary encoded drive select number. When DRV=0, Drive 0 is selected. When DRV=1, Drive 1 is selected. - HS3 through HS0 contain the binary coded address of the head to be selected e.g. if HS3 through HS0 are 0011b, respectively, head 3 will be selected. HS3 is the most significant bit. At command completion, this register is updated to reflect the currently selected head. 7.2.12 Sector Number Register In CHS Mode this register contains the starting sector number for any disk data access for the subsequent command. The sector number may be from 1 to the maximum number of sectors per track. *In LBA Mode this register contains the bits 7_0 (Byte 0) of the 28 bit LBA *for any disk access. At the end of the command, this register is updated to *reflect the current LBA bits 7_0 (Byte 0). 9.9 Identify Drive The Identify Drive command enables the host to receive parameter information from the drive. When the command is issued, the drive sets BSY, stores the required parameter information in the sector buffer, sets DRQ, and generates an interrupt. The host then reads the information out of the sector buffer. The parameter words in the buffer have the arrangement and meanings defined in Table 9-3. All reserved bits or words shall be zero. +-------+ TABLE 9-3: IDENTIFY DRIVE INFORMATION (1) | Word | +-------+------------------------------------------------------------------+ | 0 | General configuration bit-significant information: | | | 15 0 reserved for non-magnetic drives | | | 14 1=format speed tolerance gap required | | | 13 1=track offset option available | | | 12 1=data strobe offset option available | | | 11 1=rotational speed tolerance is > 0.5% | | | 10 1=disk transfer rate > 10 Mbs | | | 9 1=disk transfer rate > 5Mbs but <= 10Mbs | | | 8 1=disk transfer rate <= 5Mbs | | | 7 1=removable cartridge drive | | | 6 1=fixed drive | | | 5 1=spindle motor control option implemented | | | 4 1=head switch time > 15 usec | | | 3 1=not MFM encoded | | | 2 1=soft sectored | | | 1 1=hard sectored | | | 0 0=reserved | | 1 | Number of cylinders | | 2 | reserved | | 3 | Number of heads | | 4 | Number of unformatted bytes per track | | 5 | Number of unformatted bytes per sector | | 6 | Number of sectors per track | | 7-9 | Vendor Unique | | 10-19 | Serial number (20 ASCII characters, 0000h=not specified) | | 20 | Buffer type | | 21 | Buffer size in 512 byte increments (0000h=not specified) | | 22 | # of ECC bytes passed on Read/Write Long cmds (0000h=not spec'd) | | 23-26 | Firmware revision (8 ASCII characters, 0000h=not specified) | | 27-46 | Model number (40 ASCII characters, 0000h=not specified) | +-------+------------------------------------------------------------------+ +-------+ TABLE 9-3: IDENTIFY DRIVE INFORMATION (2) | Word | +-------+------------------------------------------------------------------+ | 47 | 15-8 Vendor Unique | | | 7-0 00h = Read/Write Multiple commands not implemented | | | xxh = Maximum number of sectors that can be transferred | | | per interrupt on Read and Write Multiple commands | | 48 | 0000h = cannot perform doubleword I/O | | | 0001h = can perform doubleword I/O | | 49 | Capabilities | *| | 15-10 0=reserved | *| | 9 1=LBA Supported | | | 8 1=DMA Supported | | | 7-0 Vendor Unique | | 50 | reserved | | 51 | 15-8 PIO data transfer cycle timing mode | | | 7-0 Vendor Unique | | 52 | 15-8 DMA data transfer cycle timing mode | | | 7-0 Vendor Unique | | 53 | 15-1 reserved | | | 0 1=the fields reported in tranlation mode are valid | | | 0=the fields reported in translation mode may be valid | | 54 | Number of current cylinders | | 55 | Number of current heads | | 56 | Number of current sectors per track | | 57-58 | Current capacity in sectors | | 59 | Current muti Size | *| 60-61 | Total Number of user addressable sectors ( LBA Mode Only ) | |128-159| Vendor Unique | |160-255| reserved | +-------+------------------------------------------------------------------+ The fields described in 9.4.1 through 9.4.5 are not affected by the Initialize Drive Parameters command. 9.9.1 Number of cylinders The number of user-addressable cylinders in the default translation mode. 9.9.2 Number of heads The number of user-addressable heads in the default translation mode. 9.9.3 Number of unformatted bytes per track The number of unformatted bytes per translated track in the default translation mode. 9.9.4 Number of unformatted bytes per sector The number of unformatted bytes per sector in the default translation mode. 9.9.5 Number of sectors per track The number of user-addressable sectors per track in the default translation mode. 9.9.6 Serial Number The contents of this field are right justified and padded with spaces (20h). 9.9.7 Buffer Type The contents of the field are determined by the manufacturer. 0000h = not specified. 0001h = a single ported single sector buffer which is not capable of simultaneous data transfers to or from the host and the disk. 0002h = a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the disk. 0003h = a dual ported multi-sector buffer capable of simultaneous transfers with a read cacheing capability. 0004-FFFFh = reserved These codes are typically not used by the operating system, however, they are useful for diagnostic programs which perform initialization routines e.g. a different interleave may be desirable for 0001h vs 0002h or 0003h. 9.9.8 Firmware Revision The contents of this field are left justified and padded with spaces (20h). 9.9.9 Model Number The contents of this field are left justified and padded with spaces (20h). 9.9.10 PIO data transfer cycle timing mode The PIO transfer timing for each ATA device falls into categories which have unique parametric timing specifications. To determine the proper device timing category, compare the Cycle Time specified in Figure 11-1 with the contents of this field. The value returned in Bits 15-8 should fall into one of the categories specified in Figure 11-1, and if it does not, then Mode 0 shall be used to serve as the default timing. 9.9.11 DMA data transfer cycle timing mode The DMA transfer timing for each ATA device falls into categories which have unique parametric timing specifications. To determine the proper device timing category, compare the Cycle Time specified in Figure 11-3 with the contents of this field. The value returned in Bits 15-8 should fall into one of the categories specified in Figure 11-3, and if it does not, then Mode 0 shall be used to serve as the default timing. 9.9.12 Number of current cylinders The number of user-addressable cylinders in the current translation mode. 9.9.13 Number of current heads The number of user-addressable heads in the current translation mode. 9.9.14 Number of current sectors per track The number of user-addressable sectors per track in the current translation mode. 9.9.15 Current capacity in sectors The current capacity in sectors excludes all sectors used for device-specific purposes. The number of sectors of available capacity may be calculated as: (Number of current cylinders * Number of current heads * Number of current sectors per track) ******************************** ADDITION STARTS ************************* 9.9.16 Drive Capacity in sectors (LBA Mode) If Drive supports LBA Mode, word 59-and word 60 will always represents total user addressable sectors. It does not depend upon the current drive geometry. ******************************** ADDITION ENDS ************************* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Following seems to be a typo error ?????? |<----------------------- t0 ---------------------->| ____________ _______ DMARQ ___/ \______________________________________/ | |<- tC ->| | |_____________________________________________ |___ DMACK- _______/ \_____/ |<--- tI --->|________________|<----- tJ -----| | DIOR-/DIOW- ____________________/ \_________________________ | | | | | |<------ tD ---->| | Read | ______________ | DD0-15 -------------------------------<______________>---------------- * | |<---tE--->|<-tE->|<-tF ->| | * *** *** Write | _________________________ | DD0-15 --------------------------<_________________________>----------- | | | | | | |<-- tG -->|<-- tH -->| | +----------------------------------+-------+-------+-------+ | DMA | Mode 0| Mode 1| Mode 2| | Timing Parameters | nsec | nsec | nsec | +----+----------------------------------+-------+-------+-------+ | t0 | Cycle Time (Min) | 960 | 480 | 240 | | tC | DMACK to DMREQ Delay (Max) | 200 | 100 | 80 | | tD | DIOR-/DIOW- 16-bit (Min) | 480 | 240 | 120 | | tE | DIOR- Data Setup (Min) | 250 | 150 | 50 | | tF | DIOR- Data Hold (Min) | 5 | 5 | 5 | | tG | DIOW- Data Setup (Min) | 250 | 100 | 35 | | tH | DIOW- Data Hold (Min) | 50 | 30 | 20 | | tI | DMACK to DIOR-/DIOW- Setup (Min) | 0 | 0 | 0 | | tJ | DIOR-/DIOW- to DMACK Hold (Min) | 0 | 0 | 0 | +----+----------------------------------+-------+-------+-------+ FIGURE 11-3: DMA DATA TRANSFER