DATE: Nov.  4, 1991                  document  X3T9.2/91-180   


  TO: X3T9.2 Committee (SCSI)

FROM: Gerry Houlder (Seagate)

SUBJECT: Question on Synchronous Transfer Agreement

I have a question for the SCSI protocol chip vendors.  Suppose I 
have a target that can do synchronous transfers of 10.0, 8.0, 
and 6.66 MB/sec in fast mode and 5.0 MB/sec in standard mode. 
Fast means the fast setup and pulse width timings are used and 
standard means the original setup and pulse width timings are 
used.

The target initiates a Synchronous Data Transfer Request (SDTR) 
message that requests 10.0 MB/sec transfers.  The initiator 
responds with a message that aggrees to 6.0 MB/sec transfers.  
This leaves the agreement at 6.0 MB/sec and "fast" timings.

Since the target cannot do 6.0 MB/sec it does the next slower 
rate (which is 5.0 MB/sec with "original" timings).  The 
initiator will be expecting 6.0 MB/sec with "fast" timing values. 
This brings me to the question: will a SCSI protocol circuit that 
is set up to receive data conforming to the "fast" timing rules 
always be able to successfully receive data that conforms to the 
"original" timing rules?

If everyone says yes, there is no problem.  However, there is 
nothing in the SCSI Standard that requires people to design their 
circuits in this way.  Will any "reasonable" design that is set 
up to expect "fast" data always work with data conforming to the 
"original" timing?  If not there may have to be wording added to 
the standard to cover this case.

I personally feel that any "reasonable" design probably will work 
OK, but I don't design SCSI protocol chips.  I would feel better 
if "real SCSI protocol chip designers" would give their opinion 
on this issue.