In section ”7.3.2 Phys originating dwords”, Table 115 lists the rate tolerance insertion rate as:

“1,5 Gbps          One deletable primitive within every 128 dwords

3 Gbps             Two deletable primitives within every 256 dwords

6 Gbps             Four deletable primitives within every 512 dwords”

My question: 

If an implementation inserts one deletable primitive every 128 dwords when running at 3 Gbps or 6 Gbps, is that phy compliant or non-compliant with this requirement?  

I can find no requirement that the two or four inserted deletable primitives be consecutive.  If they are required to be consecutive, then I think the standard should say so.

If they are not required to be consecutive, then why not just state “One deletable primitive within every 128 dwords” for all speeds?  Or are we purposefully allowing transmitting phys to hold off the insertions and then do a burst?  To what advantage?  A disadvantage is the need for (a small) amount of additional space in a speed matching FIFO if the distance between deletable primitives can be 508 dwords (at 6G).

Steve Finch

STMicroelectronics