bit ordering for SNW-3 settings

The examples in SAS2r08 Table 85, Table 86 and Table 87 each indicate that the bit ordering in Table 84 is: Bit 0 (MSB), Bit 31 (LSB).

The example given in table 87 (row 5) expands out like this:

C9FC0001h : 1100 1001 1111 1100 0000 0000 0000 0001

MSB 1: START bit T

1: Tx SSC Centre spread

00: Reserved

1001 : REQUESTED LOGICAL LINK RATE : 9h (3Gbps)

1: G1 without SSC supported

1: G2 without SSC supported

1: G3 without SSC supported

1: G1 with SSC supported

1: G2 with SSC supported

00: Reserved

0000: Reserved

000: Reserved

LSB 1: PARITY bit

I hope this clarifies the ordering.

Regards

Tim Symons
Principal Engineer
PMC-Sierra Ltd.
Burnaby

Cell: 778 998 5025
E-mail Tim_Symons@pmc-sierra.com

From: owner-t10@t10.org [mailto:owner-t10@t10.org] On Behalf Of Sheffield, Robert L
Sent: Thursday, March 22, 2007 10:17 AM
To: Day, Brian; T10 Reflector
Subject: RE: SAS 2 - bit ordering for SNW-3 settings

Intel has assumed the opposite.

Question - is the bit numbering in table-84 correct? In every other instance where bits in a field are transmitted across the wire, the first bit transmitted is the highest numbered bit in the field and is the highest order. Why is the start bit numbered "0" and not "31"? I think there's a 100% chance that breaking convention here will result in non-interoperable solutions.

Bob

From: owner-t10@t10.org [mailto:owner-t10@t10.org] On Behalf Of Day, Brian
Sent: Wednesday, March 21, 2007 1:39 PM
To: T10 Reflector
Subject: SAS 2 - bit ordering for SNW-3 settings

Any opinions to the contrary?

From: Elliott, Robert (Server Storage) [mailto:Elliott@hp.com]
Sent: Wednesday, March 21, 2007 12:10 PM
To: Day, Brian
Cc: Stephen FINCH; Tim Symons; Amr Wassal; Alvin.Cox@seagate.com
Subject: RE: bit ordering for SNW-3 settings

Good question.

Based on the bit layout proposed in 07-091 for the SMP functions, I think bit 4 should be the MSB and bit 7 should be the LSB. That way, in the SMP functions, it will have its natural encoding.

I suggest you post this Q&A to the T10 reflector to make sure nobody else has assumed the opposite.

--
Rob Elliott, elliott@hp.com
Hewlett-Packard Industry Standard Server Storage Advanced Technology
https://ecardfile.com/id/RobElliott

From: Day, Brian [mailto:Brian.Day@lsi.com]
Sent: Wednesday, March 21, 2007 11:55 AM
To: Elliott, Robert (Server Storage)
Subject: bit ordering for SNW-3 settings

Rob…

Can you clarify for me the bit ordering for the REQUESTED LOGICAL LINK RATE in the SNW-3 settings?
The example uses "9", which is the same bit flipped or not.
Would be great to get a 1.5 example added to spec too since that would show correct bit positions.

Thanks!

__________
Brian Day
LSI Logic
(719) 533-7468